In recent years, wiring substrates used for mounting of electronic components such as semiconductor chips have been decreased in size and increased in density. Japanese Laid-Open Patent Publication No. 2009-194321 describes a technique of acquiring a plurality of unit wiring substrates from a large-sized wiring substrate.
As illustrated in FIG. 18, a large-sized wiring substrate 80 includes a plurality of unit wiring substrates 81 (here, 9 unit wiring substrates) and an outer frame 82 surrounding the unit wiring substrates 81. The wiring substrate 80 is cut at cutting positions A10 and fragmentized into the unit wiring substrates 81.
An identification mark 83 that is identified as a specific character or symbol at a planar view is formed on each of the unit wiring substrates 81. In the example illustrated in FIG. 18, the identification marks 83 are identified as “B1” to “B9” at a planar view. For example, each of the identification marks 83 indicates position information or lot information of the corresponding unit wiring substrate 81. An example of a method of forming the identification mark 83 will now be described below.
First, a provisional substrate serving as a support substrate is prepared. Then, a wiring layer including a plurality of pads is formed on the provisional substrate. Then, a required number of wiring layers and a required number of insulation layers are sequentially stacked using a build-up technique, and a number of through holes are formed in the uppermost one of the insulation layers. The through holes form the identification mark 83 identifiable as a specific shape at a planar view. In the example illustrated in FIG. 18, the through holes form the identification mark 83 identifiable as, for example, “B1”.